닫기
216.73.216.213
216.73.216.213
close menu
KCI 등재
진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구
Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer
연지영 ( Ji-yeong Yeon ) , 이광선 ( Khwang-sun Lee ) , 윤성수 ( Sung-su Yoon ) , 연주원 ( Ju-won Yeon ) , 배학열 ( Hagyoul Bae ) , 박준영 ( Jun-young Park )
UCI I410-ECN-0102-2023-500-000937187

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

1. 서 론
2. 실험 방법
3. 결과 및 고찰
4. 결 론
감사의 글
REFERENCES
[자료제공 : 네이버학술정보]
×