To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on Si3N4 stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer SiO₂ capacitor.